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DS1306 serial alarm real time clock (rtc) DS1306 032598 1/20 features ? real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 ? 96 byte nonvolatile ram for data storage ? two time of day alarms programmable on com- bination of seconds, minutes, hours, and day of the week ? 1 hz and 32.768 khz clock outputs ? serial interface supports motorola serial peripheral interface (spi) serial data ports or standard 3wire interface ? burst mode for reading/writing successive addresses in clock/ram ? dual power supply pins for primary and backup power supplies ? optional trickle charge output to backup supply ? 2.0 5.5 volt operation ? optional industrial temperature range 40 c to +85 c ? available in spaceefficient 20pin tssop package ordering information DS1306 16pin dip DS1306n 16pin dip (industrial) DS1306e 20pin tssop DS1306en 20pin tssop (industrial) description the DS1306 serial alarm real time clock provides a full bcd clock calendar which is accessed via a simple serial interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. the clock operates in either the 24hour or 12hour format with am/pm indicator. in addition 96 bytes of nonvolatile ram are provided for data storage. pin assignment v bat int1 int0 32 khz v cc1 v cc2 7 1 2 3 4 5 6 8 9 DS1306 20pin tssop (173 mil) v cc2 x1 nc x2 nc int0 1 hz gnd v cc1 nc v ccif sdo sdi sclk nc sermode int1 v bat 32 khz ce 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 16 15 14 13 12 11 10 sdo sdi sclk ce x1 x2 DS1306 16pin dip (300 mil) 8 9 sermode gnd 1 hz v ccif pin description v cc1 primary power supply v cc2 backup power supply v bat +3 volt battery input v ccif interface logic power supply input gnd ground x1, x2 32,768 hz crystal connection int0 interrupt 0 output int1 interrupt 1 output sdi serial data in sdo serial data out ce chip enable sclk serial clock sermode serial interface mode
DS1306 032598 2/20 1 hz 1 hz output 32 khz 32.768 khz output an interface logic power supply input pin (v ccif ) allows the DS1306 to drive sdo and 32 khz pins to a level that is compatible with the interface logic. this allows an easy interface to 3 volt logic in mixed supply systems. the DS1306 offers dual power supplies as well as a bat- tery input pin. the dual power supplies support a pro- grammable trickle charge circuit which allows a rechargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. the v bat pin allows the device to be backed up by a nonrechargeable battery. the DS1306 is fully opera- tional from 2.0 to 5.5 volts. two programmable time of day alarms are provided by the DS1306. each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day. adon't careo states can be inserted into one or more fields if it is desired for them to be ignored for the alarm condition. a 1 hz and a 32 khz clock out- put are also available. the DS1306 supports a direct interface to motorola spi serial data ports or standard 3wire interface. an easy touse address and data format is implemented in which data transfers can occur one byte at a time or in multiple byte burst mode. operation the block diagram in figure 1 shows the main elements of the serial alarm rtc. the following paragraphs describe the function of each pin. DS1306 block diagram figure 1 ce 32.768 khz clock/calendar logic v cc input shift register user ram control registers clock, calendar, and alarm registers int0 int1 x1 x2 v cc1 v cc2 gnd sclk sdi sdo sermode power control and trickle charger serial interface v bat v ccif 1 hz 32 khz
DS1306 032598 3/20 signal descriptions v cc1 dc power is provided to the device on this pin. v cc1 is the primary power supply. v cc2 this is the secondary power supply pin. in sys- tems using the trickle charger, the rechargeable energy source is connected to this pin. v bat battery input for any standard 3 volt lithium cell or other energy source. v ccif (interface logic power supply input) the v ccif pin allows the DS1306 to drive sdo and 32 khz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3 volt logic in mixed supply systems. this pin is physically connected to the source connection of the pchannel transistors in the output buffers of the sdo and 32 khz pins. sermode (serial interface mode input) the ser- mode pin offers the flexibility to choose between two serial interface modes. when connected to gnd, stan- dard 3wire communication is selected. when con- nected to v cc , motorola spi communication is selected. sclk (serial clock input) sclk is used to synchro- nize data movement on the serial interface for either the spi or 3wire interface. sdi (serial data input) when spi communication is selected, the sdi pin is the serial data input for the spi bus. when 3wire communication is selected, this pin must be tied to the sdo pin (the sdi and sdo pins func- tion as a single i/o pin when tied together). sdo (serial data output) when spi communication is selected, the sdo pin is the serial data output for the spi bus. when 3wire communication is selected, this pin must be tied to the sdi pin (the sdi and sdo pins function as a single i/o pin when tied together). ce (chip enable) the chip enable signal must be asserted high during a read or a write for both 3wire and spi communication. this pin has an internal 55k pulldown resistor (typical). int0 (interrupt 0 output) the int0 pin is an active low output of the DS1306 that can be used as an inter- rupt input to a processor. the int0 pin can be pro- grammed to be asserted by alarm 0. the int0 pin remains low as long as the status bit causing the inter- rupt is present and the corresponding interrupt enable bit is set. the int0 pin operates when the DS1306 is powered by v cc1 , v cc2 , or v bat . the int0 pin is an open drain output and requires an external pullup resistor. 1 hz (1 hz clock output) the 1 hz pin provides a 1 hz squarewave output. this output is active when the 1 hz bit in the control register, is a logic 1. both int0 and 1 hz pins are open drain outputs. the interrupt, 1 hz signal, and the internal clock continue to run regardless of the level of v cc (as long as a power source is present). however, it is important to insure that the pullup resistors used with the pins are never pulled up to a value which is greater than vcc (x) + 0.3v. it is also required to insure that during backup operation mode, the voltage present at int0 and 1 hz does never exceed the voltage of the backup source. at all times the current on each pin should not exceed 4.0 ma at v cc = 5v, or 1.5 ma at v cc = 2.5v. int1 (interrupt 1 output) the int1 pin is an active high output of the DS1306 that can be used as an inter- rupt input to a processor. the int1 pin can be pro- grammed to be asserted by alarm 1. when an alarm condition is present, the int1 pin generates a 62.5 ms active high pulse. the int1 pin operates only when the DS1306 is powered by v cc2 or v bat . when active, the int1 pin is internally pulled up to v cc2 or v bat . when inactive, the int1 pin is internally pulled low. 32 khz (32.768 khz clock output) the 32 khz pin provides a 32.768 khz output. this signal is always present. x1, x2 connections for a standard 32.768 khz quartz crystal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pf. for more information on crystal selection and crys- tal layout considerations, please consult application note 58, acrystal considerations with dallas real time clockso. the DS1306 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated.
DS1306 032598 4/20 rtc and ram address map the address map for the rtc and ram registers of the DS1306 is shown in figure 2. data is written to the rtc by writing to address locations 80h to 9fh and is written to the ram by writing to address locations a0h to ffh. rtc data is read by reading address locations 00h to 1fh and ram data is read by reading address locations 20h to 7fh. address map figure 2 clock/calendar read addresses only 96bytes user ram read addresses only clock/calendar write addresses only 96 bytes user ram write addresses only 00h 1fh 20h 7fh 80h 9fh a0h ffh
DS1306 032598 5/20 clock, calendar, and alarm the time and calendar information is obtained by read- ing the appropriate register bytes. the real time clock registers are illustrated in figure 3. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. note that some bits are set to zero. these bits will always read 0 regardless of how they are written. also note that registers 12h to 1fh (read) and registers 92h to 9fh are reserved. these registers will always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the binarycoded decimal (bcd) format. rtc registers figure 3 bit7 bit 0 alarm 0 alarm 1 0 0 0 0 0 0 0 0 0 10 10 hr 00 12 24 a/p 10 date 10 month 10 min 10 sec sec min hours day date month 10 year m m m m m m m m 10 sec alarm 10 min alarm 12 24 10 10 hr a/p 00 0 10 sec alarm 10 min alarm 12 24 10 10 hr a/p 00 0 year sec alarm min alarm hour alarm day alarm sec alarm min alarm hour alarm day alrm control register status register trickle charger register reserved read write 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h9fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h1fh hex address range * 0059 0059 0023 0107 0131 0112 0099 0059 0059 0107 0059 0059 0107 01 12 + a/p 0023 01 12 + a/p 0023 0112 + a/p *range for alarm registers does not include mask 'm' bit
DS1306 032598 6/20 the DS1306 can be run in either 12hour or 24hour mode. bit 6 of the hours register is defined as the 12 or 24hour mode select bit. when high, the 12hour mode is selected. in the 12hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24hour mode, bit 5 is the second 10 hour bit (2023 hours). the DS1306 contains two time of day alarms. time of day alarm 0 can be set by writing to registers 87h to 8ah. time of day alarm 1 can be set by writing to regis- ters 8bh to 8eh. bit 7 of each of the time of day alarm registers are mask bits (table 1). when all of the mask bits are logic 0, a time of day alarm will only occur once per week when the values stored in timekeeping regis- ters 00h to 03h match the values stored in the time of day alarm registers. an alarm will be generated every day when bit 7 of the day alarm register is set to a logic 1. an alarm will be generated every hour when bit 7 of the day and hour alarm registers is set to a logic 1. similarly, an alarm will be generated every minute when bit 7 of the day, hour, and minute alarm registers is set to a logic 1. when bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, alarm will occur every second. time of day alarm mask bits table 1 alarm register mask bits (bit 7) seconds minutes hours days 1 1 1 1 alarm once per second 0 1 1 1 alarm when seconds match 0 0 1 1 alarm when minutes and seconds match 0 0 0 1 alarm when hours, minutes, and seconds match 0 0 0 0 alarm when day, hours, minutes, and seconds match special purpose registers the DS1306 has three additional registers (control register, status register, and trickle charger register) that control the real time clock, interrupts, and trickle charger. control register (read 0fh, write 8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 wp 0 0 0 1 hz aie1 aie0 wp (write protect) before any write operation to the clock or ram, this bit must be logic 0. when high, the write protect bit prevents a write operation to any regis- ter, including bits 0, 1, and 2 of the control register. upon initial power up, the state of the wp bit is undefined. therefore the wp bit should be cleared before attempt- ing to write to the device. 1 hz (1 hz output enable) this bit controls the 1 hz output. when this bit is a logic 1, the 1 hz output is enabled. when this bit is a logic 0, the 1 hz output is high z. aie0 (alarm interrupt enable 0) when set to a logic 1, this bit permits the interrupt 0 request flag (irqf0) bit in the status register to assert int0 . when the aie0 bit is set to logic 0, the irqf0 bit does not initiate the int0 signal. aie1 (alarm interrupt enable 1) when set to a logic 1, this bit permits the interrupt 1 request flag (irqf1) bit in the status register to assert int1. when the aie1 bit is set to logic 0, the irqf1 bit does not initiate an interrupt signal, and the int1 pin is set to a logic 0 state. status register (read 10h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 irqf1 irqf0 irqf0 (interrupt 0 request flag) a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 0 registers. if the aie0 bit is also a logic 1, the int0 pin will go low. irqf0 is cleared when any of the alarm 0 registers are read or written.
DS1306 032598 7/20 irqf1 (interrupt 1 request flag) a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 1 registers. if the aiei bit is also a logic 1, the int1 pin will generate a 62.5 ms active high pulse. irqf1 is cleared when any of the alarm 1 regis- ters are read or written. trickle charge register (read 11h, write 91h) this register controls the trickle charge characteristics of the DS1306. the simplified schematic of figure 4 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 47) control the selection of the trickle charger. in order to prevent acci- dental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. the DS1306 powers up with the trickle charger disabled. the diode select (ds) bits (bits 23) select whether one diode or two diodes are connected between v cc1 and v cc2 . if ds is 01, one diode is selected. if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger is disabled independent of tcs. the rs bits select the resistor that is connected between v cc1 and v cc2 . the resistor is selected by the resister select (rs) bits as shown in table 2. programmable trickle charger figure 4 1 of 3 select 1 of 2 select 1 of 16 select (note: only 1010 code enables charger v cc1 v cc2 trickle charger select diode select resistor select = = = tcs ds rs trickle tcs tcs tcs tcs ds ds rs rs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r1 r2 r3 2k w 4k w 8k w charge register
DS1306 032598 8/20 trickle charger resistor select table 2 rs bits resistor typical value 00 none none 01 r1 2k w 10 r2 4k w 11 r3 8k w if rs is 00, the trickle charger is disabled independent of tcs. diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 5 volts is applied to v cc1 and a super cap is connected to v cc2 . also assume that the trickle charger has been enabled with 1 diode and resister r1 between v cc1 and v cc2 . the maximum current i max would therefore be calculated as follows: i max = (5.0v diode drop)/r1 ~ (5.0v 0.7v)/2k w ~ 2.2ma obviously, as the super cap charges, the voltage drop between v cc1 and v cc2 will decrease and therefore the charge current will decrease. power control power is provided through the v cc1 , v cc2 , and v bat pins. three different power supply configurations are illustrated in figure 5. configuration 1 shows the DS1306 being backed up by a nonrechargeable energy source such as a lithium battery. in this configu- ration, the system power supply is connected to v cc1 and v cc2 is grounded. the DS1306 will be write pro- tected if v cc1 is less than v bat . configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. in this case, the v bat pin is grounded, v cc1 is connected to the primary power supply, and v cc2 is connected to the secondary supply (the rechargeable energy source). the DS1306 will operate from the larger of v cc1 or v cc2 . when v cc1 is greater than v cc2 + 0.2v (typical), v cc1 will power the DS1306. when v cc1 is less than v cc2 , v cc2 will power the DS1306. the DS1306 does not write protect itself in this configuration. configuration 3 shows the DS1306 in battery operate mode where the device is powered only by a single bat- tery. in this case, the v cc1 and v bat pins are grounded and the battery is connected to the v cc2 pin. serial interface the DS1306 offers the flexibility to choose between two serial interface modes. the DS1306 can communicate with the spi interface or with a standard 3wire inter- face. the interface method used is determined by the sermode pin. when this pin is connected to v cc , spi communication is selected. when this pin is connected to ground, standard 3wire communication is selected. serial peripheral interface (spi) the serial peripheral interface (spi) is a synchronous bus for address and data transfer and is used when interfacing with the spi bus on specific motorola micro- controllers such as the 68hc05c4 and the 68hc11a8. the spi mode of serial communication is selected by tying the sermode pin to v cc . four pins are used for the spi. the four pins are the sdo (serial data out), sdi (serial data in), ce (chip enable), and sclk (serial clock). the DS1306 is the slave device in an spi application, with the microcontroller being the master. the sdi and sdo pins are the serial data input and out- put pins for the DS1306, respectively. the ce input is used to initiate and terminate a data transfer. the sclk pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1306) devices. the shift clock (sclk), which is generated by the micro- controller, is active only during address and data trans- fer to any device on the spi bus. the inactive clock polarity is programmable in some microcontrollers. the DS1306 offers an important feature in that the level of the inactive clock is determined by sampling sclk when ce becomes active. therefore either sclk polarity can be accommodated. input data (sdi) is latched on the internal strobe edge and output data (sdo) is shifted out on the shift edge (see table 3 and figure 6). there is one clock for each bit transferred. address and data bits are transferred in groups of eight.
DS1306 032598 9/20 power supply configurations for the DS1306 figure 5 configuration 1: backup supply is a nonrechargeable lithium battery v bat v cc1 v cc2 DS1306 note: device is write protected if v cc < v bat . system v cc configuration 2: backup supply is a rechargeable battery or super capacitor v bat v cc1 v cc2 DS1306 note: device does not provide automatic write protection. primary power supply secondary power supply (rechargeable) configuration 3: battery operate mode v bat v cc1 v cc2 DS1306
DS1306 032598 10/20 function table table 3 mode ce sclk sdi sdo disable reset l input disabled input disabled high z write h cpol=1* cpol=0 data bit latch high z read h cpol=1 cpol=0 x next data bit shift** * cpol is the aclock polarityo bit that is set in the control register of the microcontroller. ** sdo remains at high z until eight bits of data are ready to be shifted out during a read. note: cpha bit polarity (if applicable) may need to be set accordingly. serial clock as a function of microcontroller clock polarity (cpol) figure 6 ce sclk ce sclk shift internal strobe shift internal strobe cpol = 1 cpol = 0 note: cpol is a bit that is set in the microcontroller's control register.
DS1306 032598 11/20 address and data bytes address and data bytes are shifted msb first into the serial data input (sdi) and out of the serial data output (sdo). any transfer requires the address of the byte to specify a write or read to either a rtc or ram location, followed by one or more bytes of data. data is trans- ferred out of the sdo for a read operation and into the sdi for a write operation (see no tag and 8). spi single byte write figure 7 ??? ?? ce sclk* sdi sdo high z a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 spi single byte read figure 8 ??? ??? ????????????? ????????????? ce sclk* sdi sdo high z a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 * sclk can be either polarity. the address byte is always the first byte entered after ce is driven high. the most significant bit (a7) of this byte determines if a read or write will take place. if a7 is 0, one or more read cycles will occur. if a7 is 1, one or more write cycles will occur. data transfers can occur one byte at a time or in multiple byte burst mode. after ce is driven high an address is written to the DS1306. after the address, one or more data bytes can be written or read. for a single byte transfer one byte is read or written and then ce is driven low. for a multiple byte transfer, however, multiple bytes can be read or written to the DS1306 after the address has been written. each read or write cycle causes the rtc register or ram address to automati- cally increment. incrementing continues until the device is disabled. when the rtc is selected, the address wraps to 00h after incrementing to 1fh (during a read) and wraps to 80h after incrementing to 9fh (during a write). when the ram is selected, the address wraps to 20h after incrementing to 7fh (during a read) and wraps to a0h after incrementing to ffh (during a write).
ce address byte data byte 0 data byte 1 data byte n sclk i/o* * i/o is sdi and sdo tied together DS1306 032598 12/20 spi multiple byte burst transfer figure 9 ??????????????? ??????????????? ????? ????? ????? ????? ????? ????? ce sclk sdi sdi sdo write read address byte data byte 0 data byte 1 data byte n address byte data byte 0 data byte 1 data byte n 3wire interface the 3wire interface mode operates similar to the spi mode. however, in 3wire mode there is one i/o instead of separate data in and data out signals. the 3wire interface consists of the i/o (sdi and sdo pins tied together), ce, and sclk pins. in 3wire mode, each byte is shifted in lsb first unlike spi mode where each byte is shifted in msb first. as is the case with the spi mode, an address byte is written to the device followed by a single data byte or multiple data bytes. figure 10 illustrates a read and write cycle. figure 11 illustrates a multiple byte burst transfer. in 3wire mode, data is input on the rising edge of sclk and output on the falling edge of sclk. 3wire single byte transfer figure 10 ce sclk i/o* a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 * i/o is sdi and sdo tied together 3wire multiple byte burst transfer figure 11
DS1306 032598 13/20 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. the dallas semiconductor DS1306 is built to the highest quality standards and manufactured for long term reliability. all dallas semiconductor devices are made using the same quality materials and manufacturing methods. however, standard versions of the DS1306 are not exposed to environmental stresses, such as burnin, that some industrial applications require. products which have successfully passed through this series of environmental stresses are marked ind or n, denoting their extended operating temperature and reliability rating. for specific reliability informa- tion on this product, please contact the factory in dallas at (972) 3714448. recommended dc operating conditions (0 c to 70 c*) parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1 , v cc2 2.0 5.5 v 1, 8 logic 1 input v ih 2.0 v cc +0.3 v 1 logic 0 input v il v cc =2.0v 0.3 +0.3 v 1 l og i c 0 i npu t v il v cc =5v 0.3 +0.8 v 1 v bat battery voltage v bat 2.0 5.5 v 1 v ccif supply voltage v ccif 2.0 5.5 v 13 dc electrical characteristics (0 c to 70 c*; v cc = 2.0 to 5.5v**) parameter symbol min typ max units notes input leakage i li +500 m a output leakage i lo 1 m a logic 0 output v ol v cc =2.0v 0.4 v 2 l og i c 0 o u t pu t v ol v cc =5v 0.4 v 2 logic 1 output v oh v ccif = 2.0v 1.6 v 12 l og i c 1 o u t pu t v oh v ccif = 5v 2.4 v 12 logic 1 output current (int1 pin) i oh , int1 (v cc2 , v bat ) 0.3v 100 m a v cc1 active supply current i cc1a v cc1 =2.0v 0.425 ma 49 v cc1 a c ti ve s upp l y c urren t i cc1a v cc1 =5v 1.28 m a 4 , 9 v cc1 timekeeping current i cc1t v cc1 =2.0v 25.3 m a 39 v cc1 ti me k eep i ng c urren t i cc1t v cc1 =5v 81 m a 3 , 9 v cc2 active supply current i cc2a v cc2 =2.0v 0.4 ma 410 v cc2 a c ti ve s upp l y c urren t i cc2a v cc2 =5v 1.2 m a 4 , 10 v cc2 timekeeping current i cc2t v cc2 =2.0v 0.4 m a 310 v cc2 ti me k eep i ng c urren t i cc2t v cc2 =5v 1 m a 3 , 10 * 40 c to +85 c for industrial device **unless otherwise noted.
DS1306 032598 14/20 dc electrical characteristics (cont'd) (0 c to 70 c*; v cc = 2.0 to 5.5v**) parameter symbol min typ max units notes battery timekeeping current i batt v bat =3v 500 na 11 trickle charge resistors r1 r2 r3 2 4 8 k w k w k w trickle charger diode voltage drop v td 0.7 v capacitance (t a = 25 c) parameter symbol condition typ max units notes input capacitance c i 10 pf output capacitance c o 15 pf crystal capacitance c x 6 pf 3wire ac electrical characteristics (0 c to 70 c*; v cc = 2.0v to 5.5v**) parameter symbol min typ max units notes data to clk setup t dc v cc =2.0v 200 ns 56 d a t a t o clk s e t up t dc v cc =5v 50 ns 5 , 6 clk to data hold t cdh v cc =2.0v 280 ns 56 clk t o d a t a h o ld t cdh v cc =5v 70 ns 5 , 6 clk to data delay t cdd v cc =2.0v 800 ns 567 clk t o d a t a d e l ay t cdd v cc =5v 200 ns 5 , 6 , 7 clk low time t cl v cc =2.0v 1000 ns 6 clk l ow t i me t cl v cc =5v 250 ns 6 clk high time t ch v cc =2.0v 1000 ns 6 clk hi g h t i me t ch v cc =5v 250 ns 6 clk frequency t clk v cc =2.0v 0.6 mhz 6 clk f requency t clk v cc =5v dc 2.0 mh z 6 clk rise and fall t r t f v cc =2.0v 2000 ns clk ri se an d f a ll t r , t f v cc =5v 500 ns * 40 c to +85 c for industrial device **unless otherwise noted.
t cc a0 a1 ce sclk i/o* a7 t cwh t cch t cdh t dc t f t r t ch t cl write address byte write data d0 * i/o is sdi and sdo tied together. DS1306 032598 15/20 3wire ac electrical characteristics (cont'd) (0 c to 70 c*; v cc = 2.0 to 5.5v**) parameter symbol min typ max units notes ce to clk setup t cc v cc =2.0v 4 m s 6 ce t o clk s e t up t cc v cc =5v 1 m s 6 clk to ce hold t cch v cc =2.0v 240 ns 6 clk t o ce h o ld t cch v cc =5v 60 ns 6 ce inactive time t cwh v cc =2.0v 4 m s 6 ce i nac ti ve t i me t cwh v cc =5v 1 m s 6 ce to output high z t cdz v cc =2.0v 280 ns 56 ce t o o u t pu t hi g h z t cdz v cc =5v 70 ns 5 , 6 sclk to output high z t ccz v cc =2.0v 280 ns 56 sclk t o o u t pu t hi g h z t ccz v cc =5v 70 ns 5 , 6 * 40 c to +85 c for industrial device **unless otherwise noted. timing diagram: 3wire read data transfer figure 12 t cc t cdd t ccz t cdh t dc a0 a1 a7 ce sclk i/o* write address byte read data bit d0 d1 t cdd t cdz timing diagram: 3wire write data transfer figure 13
DS1306 032598 16/20 spi ac electrical characteristics (0 c to 70 c*; v cc = 2.0 to 5.5v**) parameter symbol min typ max units notes data to clk setup t dc v cc =2.0v 200 ns 56 d a t a t o clk s e t up t dc v cc =5v 50 ns 5 , 6 clk to data hold t cdh v cc =2.0v 280 ns 56 clk t o d a t a h o ld t cdh v cc =5v 70 ns 5 , 6 clk to data delay t cdd v cc =2.0v 800 ns 567 clk t o d a t a d e l ay t cdd v cc =5v 200 ns 5 , 6 , 7 clk low time t cl v cc =2.0v 1000 ns 6 clk l ow t i me t cl v cc =5v 250 ns 6 clk high time t ch v cc =2.0v 1000 ns 6 clk hi g h t i me t ch v cc =5v 250 ns 6 clk frequency t clk v cc =2.0v 0.6 mhz 6 clk f requency t clk v cc =5v dc 2.0 mh z 6 clk rise and fall t r t f v cc =2.0v 2000 ns clk ri se an d f a ll t r , t f v cc =5v 500 ns ce to clk setup t cc v cc =2.0v 4 m s 6 ce t o clk s e t up t cc v cc =5v 1 m s 6 clk to ce hold t cch v cc =2.0v 240 ns 6 clk t o ce h o ld t cch v cc =5v 60 ns 6 ce inactive time t cwh v cc =2.0v 4 m s 6 ce i nac ti ve t i me t cwh v cc =5v 1 m s 6 ce to output high z t cdz v cc =2.0v 280 ns 56 ce t o o u t pu t hi g h z t cdz v cc =5v 70 ns 5 , 6 * 40 c to +85 c for industrial device **unless otherwise noted.
DS1306 032598 17/20 timing diagram: spi read data transfer figure 14 t cc t cdh t dc a7 a6 a0 ce sclk* sdi sdo d7 d6 d1 d0 t cdz t cdd write address byte read data byte t cdd timing diagram: spi write data transfer figure 15 t cc a7 a6 ce sclk* sdi a0 t cwh t cdh t cdh t dc t f t r t ch t cl write address byte write data byte d7 d0 t cch * sclk can be either polarity, timing shown for cpol = 1.
DS1306 032598 18/20 notes: 1. all voltages are referenced to ground. 2. logic zero voltages are specified at a sink current of 4 ma at v cc =5v and 1.5 ma at v cc =2.0v, v ol =gnd for capacitive loads. 3. i cc1t and i cc2t are specified with ce set to a logic 0. 4. i cc1a and i cc2a are specified with ce=v cc , sclk=2 mhz (0v cc ) at v cc =5v; sclk=500 khz (0v cc ) at v cc =2.0v. 5. measured at v ih =2.0v or v il =0.8v and 10 ms maximum rise and fall time. 6. measured with 50 pf load. 7. measured at v oh =2.4v or v ol =0.4v. 8. v cc =v cc1 , when v cc1 >v cc2 +0.2v (typical); v cc =v cc2 , when v cc2 >v cc1 . 9. v cc2 =0 volts. 10. v cc1 =0 volts. 11. (v cc1 =v cc2 ) < v bat . 12. logic one voltages are specified at a source current of 1 ma at v cc =5v and 0.4 ma at 2.0v, v oh =v cc for capaci- tive loads. 13. v ccif must be less than or equal to the largest of v cc1 , v cc2 , and v bat .
DS1306 032598 19/20 DS1306 16pin dip (300 mil) a b c e f g h j k d 1 pkg 16pin dim min max a in. mm 0.740 18.80 0.780 19.81 b in. mm 0.240 6.10 0.260 6.60 c in. mm 0.120 3.05 0.140 3.56 d in. mm 0.300 7.62 0.325 8.26 e in. mm 0.015 0.38 0.040 1.02 f in. mm 0.120 3.04 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in mm 0.320 8.13 0.370 9.40 j in mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53
DS1306 032598 20/20 DS1306 20pin tssop d h e see detail a detail a a1 a b l g e1 c phi n a2 dim min max a mm 1.10 a1 mm 0.05 a2 mm 0.75 1.05 c mm 0.09 0.18 l mm 0.50 0.70 e1 mm 0.65 bsc b mm 0.18 0.30 d mm 6.40 6.90 e mm 4.40 nom g mm 0.25 ref h mm 6.25 6.55 phi 0 8

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